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lt1801/lt1802 1 18012fc typical application description l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications dual/quad 80mhz, 25v/s low power rail-to-rail input and output precision op amps the lt ? 1801/lt1802 are dual/quad, low power, high speed rail-to-rail input and output operational ampli? ers with excellent dc performance. the lt1801/lt1802 feature reduced supply current, lower input offset voltage, lower input bias current and higher dc gain than other devices with comparable bandwidth. typically, the lt1801/lt1802 have an input offset voltage of less than 10 0 v, an input bias current of less than 50n a and an open-loop gain of 85 thousand. the lt1801/lt1802 have an input range that includes both supply rails and an output that swings within 20mv of either supply rail to ma ximize the signal dynamic range in low supply applications. the lt1801/lt1802 maintain their performance for sup- plies from 2.3v to 12.6v and are speci? ed at 3v, 5v and 5v supplies. the inputs can be driven beyond the supplies without damage or phase reversal of the output. the lt1801 is available in the ms8, so-8 and the 3mm 3mm 0.8mm dual ? ne pitch leadless package (dfn) with the standard dual op amp pinout. the lt1802 features the standard quad op amp con? guration and is available in the 14-pin plastic so package. the lt1801/lt1802 can be used as plug-in replacements for many op amps to improve input/output range and performance. for a single version of these ampli? ers, see the lt1800 data sheet. n gain bandwidth product: 80mhz n input common mode range includes both rails n output swings rail-to-rail n low voltage operation: single or split supplies 2.3v to 12.6v n low quiescent current: 2ma/ampli? er max n input offset voltage: 350v max n input bias current: 250na max n 3mm 3mm 0.8mm dfn package n large output current: 50ma typ n low voltage noise: 8.5nv/ hz typ n slew rate: 25v/s typ n common mode rejection: 105db typ n power supply rejection: 97db typ n open-loop gain: 85v/mv typ n operating temperature range: C 40c to 85c n lt1801 is available in 8-lead so, ms8 and dfn packages n lt1802 is available in 14-lead so package n low voltage, high frequency signal processing n driving a/d converters n rail-to-rail buffer ampli? ers n active filters n video line driver C + 1/2 lt1801 47pf 220pf v in v s /2 909 2.67k 909 C + 1/2 lt1801 22pf v out 470pf 18012 ta01 1.1k 2.21k 3v 1.1k 3v, 1mhz, 4th order butterworth filter frequency (hz) ?80 gain (db) ?40 0 ?100 ?60 ?20 1k 100k 1m 10m 100m 18012 ta02 ?120 10k 1mhz filter frequency response
lt1801/lt1802 2 18012fc pin configuration absolute maximum ratings (note 1) order information total supply voltage (v s C to v s + ) ......................... 12.6v input current (note 2) ......................................... 10ma output short-circuit duration (note 3) ........... inde? nite operating temperature range (note 4) ..C40c to 85c speci? ed temperature range (note 5) ....C40c to 85c junction temperature .......................................... 150c storage temperature range .................. C65c to 150c maximum junction temperature (dd package) .... 125c storage temperature (dd package) ....... C65c to 125c lead temperature msop, soic (soldering, 10 sec) ............................................ 300c lead free finish tape and reel part marking* package description operating temperature range lt1801cdd#pbf lt1801cdd#trpbf la am 8-lead (3mm 3mm) plastic dfn C40c to 85c lt1801idd#pbf lt1801idd#trpbf laam 8-lead (3mm 3mm) plastic dfn C40c to 85c lt1801cms8#pbf lt1801cms8#trpbf lt yr 8-lead plastic msop C40c to 85c lt1801ims8#pbf lt1801ims8#trpbf lt ys 8-lead plastic msop C40c to 85c lt1801cs8#pbf lt1801cs8#trpbf 1801 8-lead plastic so C40c to 85c lt1801is8#pbf lt1801is8#trpbf 1801i 8-lead plastic so C40c to 85c lt1802cs#pbf lt1802cs#trpbf lt1802cs 14-lead plastic so C40c to 85c lt1802is#pbf lt1802is#trpbf lt1802is 14-lead plastic so C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a l abel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ top view dd package 8-lead ( 3mm 3mm ) plastic dfn 5 6 7 8 4 3 2 1 out a Cin a +in a v C v + out b Cin b +in b b a 1 2 3 4 out a Cin a +in a v C 8 7 6 5 v + out b Cin b +in b top view ms8 package 8-lead plastic msop t jmax = 125c, ja = 160c/w, (note 10) exposed pad internally connected to v C . (pcb connection optional) t jmax = 150c, ja = 250c/w, (note 10) 1 2 3 4 8 7 6 5 top view v + out b Cin b +in b out a Cin a +in a v C s8 package 8-lead plastic so + C + C top view s package 14-lead plastic so 1 2 3 4 5 6 7 14 13 12 11 10 9 8 out a Cin a +in a v + +in b Cin b out b out d Cin d +in d v C +in c Cin c out c a bc d t jmax = 150c, ja = 190c/w, (note 10) t jmax = 150c, ja = 160c/w, (note 10)
lt1801/lt1802 3 18012fc electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = 0v v cm = 0v (ms8) v cm = 0v (dd) v cm = v s 75 140 175 0.5 350 500 800 3 v v v mv v os input offset shift v cm = 0v to v s C 1.5v 20 185 v input offset voltage match (channel-to-channel) (note 9) v cm = 0v v cm = 0v (ms8) v cm = 0v (dd) 100 150 280 650 900 1200 v v v i b input bias current v cm = 1v v cm = v s 25 500 250 1500 na na input bias current match (channel-to-channel) (note 9) v cm = 1v v cm = v s 25 25 350 500 na na i os input offset current v cm = 1v v cm = v s 25 25 200 200 na na input noise voltage 0.1hz to 10hz 1.4 v p-p e n input noise voltage density f = 10khz 8.5 nv/ hz i n input noise current density f = 10khz 1 pa/ hz c in input capacitance 2pf a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k at v s /2 v s = 5v, v o = 1v to 4v, r l = 100 at v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k at v s /2 35 3.5 30 85 8 85 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = 0v to 3.5v v s = 3v, v cm = 0v to 1.5v 85 78 105 97 db db cmrr match (channel-to-channel) (note 9) v s = 5v, v cm = 0v to 3.5v v s = 3v, v cm = 0v to 1.5v 79 72 105 97 db db input common mode range 0 v s v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 78 97 db psrr match (channel-to-channel) (note 9) v s = 2.5v to 10v, v cm = 0v 72 97 db minimum supply voltage (note 6) 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 20ma 16 85 225 60 200 500 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 20ma 18 120 450 60 250 800 mv mv mv i sc short-circuit current v s = 5v v s = 3v 20 20 45 40 ma ma i s supply current per ampli? er 1.6 2 ma gbw gain bandwidth product frequency = 2mhz 40 80 mhz sr slew rate v s = 5v, a v = C 1, r l = 1k, v o = 1v to 4v 12.5 25 v/s fpbw full power bandwidth v s = 5v, a v = 1, v o = 4v p-p 2mhz hd harmonic distortion v s = 5v, a v = 1, r l = 1k, v o = 2v p-p , f c = 500khz C75 dbc t s settling time 0.01%, v s = 5v, v step = 2v, a v = 1, r l = 1k 250 ns g differential gain (ntsc) v s = 5v, a v = 2, r l = 150 0.35 % differential phase (ntsc) v s = 5v, a v = 2, r l = 150 0.4 deg t a = 25c, v s = 5v, 0v; v s = 3v, 0v; v cm = v out = half supply, unless otherwise noted.
lt1801/lt1802 4 18012fc electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = 0v v cm = 0v (ms8) v cm = 0v (dd) v cm = v s l l l l 125 140 290 0.6 500 650 950 3.5 v v v mv v os input offset shift v cm = 0v to v s C 1.5v l 30 275 v input offset voltage match (channel-to-channel) (note 9) v cm = 0v v cm = 0v (ms8) v cm = 0v (dd) l l l 200 200 275 850 1250 1500 v v v v os tc input offset voltage drift (note 8) l 1.5 5 v/c i b input bias current v cm = 1v v cm = v s C 0.2v l l 50 550 300 2000 na na input bias current match (channel-to-channel) (note 9) v cm = 1v v cm = v s C 0.2v l l 25 25 400 600 na na i os input offset current v cm = 1v v cm = v s C 0.2v l l 25 25 300 300 na na a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k at v s /2 v s = 5v, v o = 1v to 4v, r l = 100 at v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k at v s /2 l l l 25 2.5 20 75 6 75 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = 0v to 3.5v v s = 3v, v cm = 0v to 1.5v l l 82 74 101 93 db db cmrr match (channel-to-channel) (note 9) v s = 5v, v cm = 0v to 3.5v v s = 3v, v cm = 0v to 1.5v l l 76 68 101 93 db db input common mode range l 0v s v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 74 91 db psrr match (channel-to-channel) (note 9) v s = 2.5v to 10v, v cm = 0v l 68 91 db minimum supply voltage (note 6) l 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 20ma l l l 18 100 300 80 225 600 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 20ma l l l 25 150 600 80 300 950 mv mv mv i sc short-circuit current v s = 5v v s = 3v l l 20 15 40 30 ma ma i s supply current per ampli? er l 22.8 ma gbw gain bandwidth product frequency = 2mhz l 35 75 mhz sr slew rate v s = 5v, a v = C 1, r l = 1k, v o = 1v to 4v l 11 22 v/s the l denotes the speci? cations which apply over the temperature range of 0c < t a < 70c. v s = 5v, 0v; v s = 3v, 0v; v cm = v out = half supply, unless otherwise noted.
lt1801/lt1802 5 18012fc electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = 0v v cm = 0v (ms8) v cm = 0v (dd) v cm = v s l l l l 175 200 320 0.75 700 850 1150 4 v v v mv v os input offset shift v cm = 0v to v s C 1.5v l 30 300 v input offset voltage match (channel-to-channel) (note 9) v cm = 0v v cm = 0v (ms8) v cm = 0v (dd) l l l 200 280 320 1250 1600 1800 v v v v os tc input offset voltage drift (note 8) l 1.5 5 v/c i b input bias current v cm = v s C 0.2v l l 50 600 400 2250 na na input bias current match (channel-to-channel) (note 9) v cm = 1v v cm = v s C 0.2v l l 25 25 450 700 na na i os input offset current v cm = 1v v cm = v s C 0.2v l l 25 25 350 350 na na a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k at v s /2 v s = 5v, v o = 1.5v to 3.5v, r l = 100 at v s /2 v s = 3v, v o = 0.5v to 2.5v, r l = 1k at v s /2 l l l 20 2 17.5 65 6 65 v/mv v/mv v/mv cmrr common mode rejection ratio v s = 5v, v cm = 0v to 3.5v v s = 3v, v cm = 0v to 1.5v l l 81 73 101 93 db db cmrr match (channel-to-channel) (note 9) v s = 5v, v cm = 0v to 3.5v v s = 3v, v cm = 0v to 1.5v l l 75 67 101 93 db db input common mode range l 0v s v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 73 90 db psrr match (channel-to-channel) (note 9) v s = 2.5v to 10v, v cm = 0v l 67 90 db minimum supply voltage (note 6) v cm = v o = 0.5v l 2.3 2.5 v v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 10ma l l l 15 105 170 90 250 400 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 10ma l l l 25 150 300 90 350 700 mv mv mv i sc short-circuit current v s = 5v v s = 3v l l 12.5 12.5 30 30 ma ma i s supply current per ampli? er l 2.1 3 ma gbw gain bandwidth product frequency = 2mhz l 25 70 mhz sr slew rate v s = 5v, a v = C 1, r l = 1k, v o = 1v to 4v l 918 v/s the l denotes the speci? cations which apply over the temperature range of C 40c < t a < 85c. v s = 5v, 0v; v s = 3v, 0v; v cm = v out = half supply, unless otherwise noted. (note 5)
lt1801/lt1802 6 18012fc electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v s C v cm = v s C (ms8) v cm = v s C (dd) v cm = v s + 150 180 260 0.7 600 750 1050 3.5 v v v mv v os input offset shift v cm = v s C to v s + C 1.5v 30 475 v input offset voltage match (channel-to-channel) (note 9) v cm = v s C v cm = v s C (ms8) v cm = v s C (dd) 150 275 325 1000 1300 1600 v v v i b input bias current v cm = v s C + 1v v cm = v s + 25 400 250 1500 na na input bias current match (channel-to-channel) (note 9) v cm = v s C + 1v v cm = v s + 20 20 350 500 na na i os input offset current v cm = v s C + 1v v cm = v s + 20 20 250 250 na na input noise voltage 0.1hz to 10hz 1.4 v/ p-p e n input noise voltage density f = 10khz 8.5 nv/ hz i n input noise current density f = 10khz 1 pa/ hz c in input capacitance f = 100khz 2 pf a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2v to 2v, r l = 100 25 2.5 70 7 v/mv v/mv cmrr common mode rejection ratio v cm = v s C to 3.5v 85 109 db cmrr match (channel-to-channel) (note 9) v cm = v s C to 3.5v 79 109 db input common mode range v s C v s + v psrr power supply rejection ratio v s + = 2.5v to 10v, v s C = 0v 78 97 db psrr match (channel-to-channel) (note 9) v s + = 2.5v to 10v, v s C = 0v 72 97 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 20ma 15 90 225 70 200 500 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 20ma 20 130 450 80 260 850 mv mv mv i sc short-circuit current 25 50 ma i s supply current per ampli? er 1.8 3 ma gbw gain bandwidth product frequency = 2mhz 70 mhz fpbw full power bandwidth v o = 8v p-p 0.9 mhz sr slew rate a v = C 1, r l = 1k, v o = 4v, measured at v o = 2v 20 v/s hd harmonic distortion a v = 1, r l = 1k, v o = 2v p-p , f c = 500khz C75 dbc t s settling time 0.01%, v step = 5v, a v = 1v, r l = 1k 300 ns g differential gain (ntsc) a v = 2, r l = 150 0.35 % differential phase (ntsc) a v = 2, r l = 150 0.2 deg t a = 25c, v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted.
lt1801/lt1802 7 18012fc electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v s C v cm = v s C (ms8) v cm = v s C (dd) v cm = v s + l l l l 200 220 290 0.75 800 1000 1300 4 v v v mv v os input offset shift v cm = v s C to v s + C 1.5v l 45 675 v input offset voltage match (channel-to-channel) (note 9) v cm = v s C v cm = v s C (ms8) v cm = v s C (dd) l l l 240 300 340 1500 1700 1950 v v v v os tc input offset voltage drift (note 8) l 1.5 5 v/c i b input bias current v cm = v s C + 1v v cm = v s + C 0.2v l l 30 450 300 2000 na na input bias current match (channel-to-channel) (note 9) v cm = v s C + 1v v cm = v s + C 0.2v l l 25 25 400 700 na na i os input offset current v cm = v s C + 1v v cm = v s + C 0.2v l l 25 25 300 300 na na a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C2v to 2v, r l = 100 l l 15 2 55 5 v/mv v/mv cmrr common mode rejection ratio v cm = v s C to 3.5v l 82 105 db cmrr match (channel-to-channel) (note 9) v cm = v s C to 3.5v l 76 105 db input common mode range l v s C v s + v psrr power supply rejection ratio v s + = 2.5v to 10v, v s C = 0v l 74 91 db psrr match (channel-to-channel) (note 9) v s + = 2.5v to 10v, v s C = 0v l 68 93 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 20ma l l l 17 105 250 80 250 575 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 20ma l l l 25 150 600 90 310 975 mv mv mv i sc short-circuit current l 22.5 45 ma i s supply current per ampli? er l 2.4 4 ma gbw gain bandwidth product frequency = 2mhz l 70 mhz sr slew rate a v = C 1, r l = 1k, v o = 4v, measured at v o = 2v l 20 v/s symbol parameter conditions min typ max units v os input offset voltage v cm = v s C v cm = v s C (ms8) v cm = v s C (dd) v cm = v s + l l l l 350 350 350 0.75 1000 1200 1500 5 v v v mv v os input offset shift v cm = v s C to v s + C 1.5v l 50 750 v input offset voltage match (channel-to-channel) (note 9) v cm = v s C v cm = v s C (ms8) v cm = v s C (dd) l l l 280 380 410 1700 1900 2100 v v v the l denotes the speci? cations which apply over the temperature range of 0c < t a < 70c. v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted. the l denotes the speci? cations which apply over the temperature range of C 40c < t a < 85c. v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted. (note 5)
lt1801/lt1802 8 18012fc electrical characteristics symbol parameter conditions min typ max units v os tc input offset voltage drift (note 8) l 1.5 5 v/c i b input bias current v cm = v s C + 1v v cm = v s + C 0.2v l l 50 450 400 2250 na na input bias current match (channel-to-channel) (note 9) v cm = v s C + 1v v cm = v s + C 0.2v l l 25 25 450 700 na na i os input offset current v cm = v s C + 1v v cm = v s + C 0.2v l l 25 25 350 350 na na a vol large-signal voltage gain v o = C4v to 4v, r l = 1k v o = C1v to 1v, r l = 100 l l 12.5 2 55 5 v/mv v/mv cmrr common mode rejection ratio v cm = v s C to 3.5v l 81 104 db cmrr match (channel-to-channel) (note 9) v cm = v s C to 3.5v l 75 104 db input common mode range l v s C v s + v psrr power supply rejection ratio v s + = 2.5v to 10v, v s C = 0v l 73 90 db psrr match (channel-to-channel) (note 9) v s + = 2.5v to 10v, v s C = 0v l 67 90 db v ol output voltage swing low (note 7) no load i sink = 5ma i sink = 10ma l l l 20 110 180 100 275 400 mv mv mv v oh output voltage swing high (note 7) no load i source = 5ma i source = 10ma l l l 30 150 300 110 350 700 mv mv mv i sc short-circuit current l 12.5 30 ma i s supply current per ampli? er l 2.6 4.5 ma gbw gain bandwidth product frequency = 2mhz l 65 mhz sr slew rate a v = C 1, r l = 1k, v o = 4v, measured at v o = 2v l 15 v/s the l denotes the speci? cations which apply over the temperature range of C 40c < t a < 85c. v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. it is not 100% tested. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 4: the lt1 8 01c/lt1 8 01i and lt1 8 02c/lt1 8 02i are guaranteed functional over the temperature range of ? 40c to 8 5c. note 5: the lt1 8 01c/lt1 8 02c are guaranteed to meet speci? ed performance from 0c to 70c. the lt1 8 01c/lt1 8 02c are designed, characterized and expected to meet speci? ed performance from ?40c to 8 5c but are not tested or qa sampled at these temperatures. the lt1 8 01i/lt1 8 02i are guaranteed to meet speci? ed performance from ?40c to 8 5c. note 6: minimum supply voltage is guaranteed by power supply rejection ratio test. note 7: output voltage swings are measured between the output and power supply rails. note 8: this parameter is not 100% tested. note 9: matching parameters are the difference between ampli? ers a and d and between b and c on the lt1 8 02; between the two ampli? ers on the lt1 8 01. note 10: thermal resistance ( ja ) varies with the amount of pc board metal connected to the package. the speci? ed values are for short traces connected to the leads. if desired, the thermal resistance can be substantially reduced by connecting pin 4 of the so- 8 and ms 8 , pin 11 of the so-14 or the underside metal of the dd package to a larger metal area (v s ? trace).
lt1801/lt1802 9 18012fc typical performance characteristics supply current vs supply voltage offset voltage vs input common mode voltage input bias current vs common mode voltage input bias current vs temperature output saturation voltage vs load current (output low) v os distribution, v cm = 0v (pnp stage) v os distribution, v cm = 5v (npn stage) input offset voltage (v) C250 0 percent of units (%) 5 15 20 25 50 150 35 18012 g01 10 C150 C50 250 30 v s = 5v, 0v v cm = 0v input offset voltage (v) C2000 0 percent of units (%) 5 15 20 25 400 1200 45 18012 g02 10 C1200 C400 2000 30 35 40 v s = 5v, 0v v cm = 5v total supply voltage (v) 1 0 supply current (ma) 3 12 18012 g03 0 357910 2468 11 4 2 1 t a = 125c t a = 25c t a = C55c per amplifier input common mode voltage (v) 0 offset voltage (v) 100 300 500 4 18012 g04 C100 C300 0 200 400 C200 C400 C500 1 2 3 5 v s = 5v, 0v typical part t a = C55c t a = 125c t a = 25c input common mode voltage (v) C1 input bias current (a) 0.2 0.6 1.0 4 18012 g05 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 0 1 23 5 6 v s = 5v, 0v t a = 25c t a = 125c t a = C55c temperature (c) C60 C0.1 input bias (a) 0 0.2 0.3 0.4 40 60 80 0.8 18012 g06 0.1 C40 C20 0 20 0.5 0.6 0.7 npn active v s = 5v, 0v v cm = 5v pnp active v s = 5v, 0v v cm = 1v load current (ma) 0.01 0.1 0.001 output saturation voltage (v) 0.1 10 1 10 100 18012 g07 0.01 1 v s = 5v, 0v t a = 125c t a = C55c t a = 25c output saturation voltage vs load current (output high) load current (ma) 0.01 0.1 0.001 output saturation voltage (v) 0.1 10 1 10 100 18012 g08 0.01 1 v s = 5v, 0v t a = 125c t a = C55c t a = 25c
lt1801/lt1802 10 18012fc typical performance characteristics open-loop gain open-loop gain offset voltage vs output current warm-up drift vs time open-loop gain output short-circuit current vs power supply voltage input noise voltage vs frequency power supply voltage (v) 1.5 C70 output short-circuit current (ma) C50 C30 C10 70 30 2 3 3.5 5 50 10 C60 C40 C20 60 20 40 0 2.5 4 4.5 t a = 125c t a = 125c t a = C55c sinking sourcing t a = C55c t a = 25c t a = 25c 18012 g10 output voltage (v) 0 C2000 change in offset voltage (v) C1200 C400 400 0.5 1 1.5 2 18012 g11 2.5 1200 2000 C1600 C800 0 800 1600 3 v s = 3v, 0v r l to gnd r l = 1k r l = 100 output voltage (v) 0 change in offset voltage (v) 400 1200 2000 4 18012 g12 C400 C1200 0 800 1600 C800 C1600 C2000 1 0.5 2 1.5 3 3.5 4.5 2.5 5 v s = 5v, 0v r l to gnd r l = 1k r l = 100 output voltage (v) C5 change in offset voltage (v) 400 1200 2000 3 18012 g13 C400 C1200 0 800 1600 C800 C1600 C2000 C3 C4 C1 C2 12 4 0 5 v s = 5v r l to gnd r l = 1k r l = 100 output current (ma) C60 change in offset voltage (mv) 0 1.0 60 18012 g14 C1.0 C2.0 C30 0 30 C45 C15 15 45 2.0 C0.5 0.5 C1.5 1.5 v s = 5v t a = 125c t a = C55c t a = 25c time after power-up (seconds) 0 offset voltage (v) 110 60 18012 g15 80 60 20 40 80 50 40 120 100 90 70 100 120 140 v s = 5v v s = 2.5v v s = 1.5v typical part frequency (khz) 20 noise voltage (nv/hz) 40 60 10 30 50 0.01 1 10 100 18012 g16 0 0.1 v s = 5v, 0v npn active v cm = 4.25v pnp active v cm = 2.5v minimum supply voltage total supply voltage (v) 0 C0.6 change in offset voltage (mv) C0.4 0 0.2 0.4 2 3 3.5 5.5 18012 g09 C0.2 1.5 2.5 4 4.5 5 0.6 t a = 125c t a = C55c t a = 25c
lt1801/lt1802 11 18012fc typical performance characteristics gain bandwidth and phase margin vs supply voltage gain bandwidth and phase margin vs temperature slew rate vs temperature gain and phase vs frequency gain vs frequency (a v = 1) gain vs frequency (a v = 2) total supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 100 90 80 70 60 60 50 40 30 20 8 18012 g19 246 10 7 135 9 gain bandwidth product phase margin t a = 25c temperature (c) C55 gain bandwidth (mhz) phase margin (deg) 50 100 70 C15 25 45 125 18012 g20 80 90 60 10 20 40 50 60 30 C35 5 65 85 105 gbw product v s = 2.5v phase margin v s = 2.5v phase margin v s = 5v gbw product v s = 5v temperature (c) C55 10 slew rate (v/s) 15 25 30 35 C15 25 45 125 18012 g21 20 C35 5 65 85 105 a v = C1 r f = r g = 1k r l = 1k v s = 2.5v v s = 5v frequency (mhz) 0.01 10 open-loop gain (db) phase (deg) 20 30 40 50 0.1 1 10 100 300 18012 g22 0 C40 C10 C20 C30 60 70 C20 0 20 40 60 C60 C80 C100 80 100 v s = 2.5v v s = 5v phase gain frequency (mhz) C6 gain (db) 0 3 9 12 0.1 10 100 300 18012 g23 C12 1 6 C3 C9 r l = 1k c l = 10pf a v = 1 v s = 5v v s = 2.5v frequency (mhz) 0 gain (db) 6 9 15 18 0.1 10 100 300 18012 g24 C6 1 12 3 C3 r l = 1k c l = 10pf a v = 2 v s = 5v v s = 2.5v 0.1hz to 10hz input voltage input current noise vs frequency frequency (khz) 1.0 noise current (pa/hz) 2.0 3.0 0.5 1.5 2.5 0.01 1 10 100 18012 g17 0 0.1 v s = 5v, 0v npn active v cm = 4.25v pnp active v cm = 2.5v time (seconds) 0 input noise voltage (nv) 2000 1000 0 C1000 C2000 8 18012 g18 246 10 7 135 9 v s = 5v, 0v
lt1801/lt1802 12 18012fc series output resistor vs capacitive load distortion vs frequency distortion vs frequency maximum undistorted output signal vs frequency capacitive load (pf) 10 20 overshoot (%) 30 40 100 1000 10000 18012 g29 10 0 60 50 15 25 35 5 55 45 v s = 5v, 0v a v = 2 r os = 10 r os = r l = 50 r os = 20 frequency (mhz) 0.01 C70 distortion (dbc) C60 C50 C40 0.1 1 10 18012 g30 C80 C90 C100 C110 v s = 5v, 0v a v = 1 v out = 2v p-p r l = 150, 2nd r l = 1k, 2nd r l = 1k, 3rd r l = 150, 3rd frequency (mhz) 0.01 C70 distortion (dbc) C60 C50 C40 0.1 1 10 18012 g31 C80 C90 C100 C110 v s = 5v, 0v a v = 2 v out = 2v p-p r l = 150, 2nd r l = 150, 3rd r l = 1k, 2nd r l = 1k, 3rd frequency (hz) 4.1 output voltage swing (v p-p ) 4.3 4.5 4.6 1k 100k 1m 10m 18012 g32 3.9 10k 4.4 4.2 4.0 v s = 5v, 0v r l = 1k a v = C1 a v = 2 series output resistor vs capacitive load capacitive load (pf) 10 20 overshoot (%) 30 40 100 1000 10000 18012 g28 10 0 60 50 15 25 35 5 55 45 v s = 5v, 0v a v = 1 r os = 10 r os = 20 r os = r l = 50 power supply rejection ratio vs frequency frequency (mhz) 0.001 30 power supply rejection ratio (db) 40 50 60 70 0.01 0.1 1 10 100 18012 g27 20 10 0 C10 80 90 v s = 5v, 0v t a = 25c positive supply negative supply output impedance vs frequency common mode rejection ratio vs frequency frequency (mhz) 0.1 0.001 output impedance () 0.1 600 100 1 10 100 500 18012 g25 0.01 1 10 v s = 2.5v a v = 10 a v = 1 a v = 2 frequency (mhz) 40 common mode rejection ratio (db) 80 120 20 60 100 0.01 1 10 100 18012 g26 0 0.1 v s = 5v, 0v typical performance characteristics
lt1801/lt1802 13 18012fc 5v small-signal response 50mv/div v s = 5v 50ns/div 18012 g36 a v = 1 r l = 1k 0v output overdriven recovery v in 1v/div v s = 5v, 0v 100ns/div 18012 g37 a v = 2 r l = 1k 0v v out 2v/div 5v large-signal response 2v/div v s = 5v 200ns/div 18012 g35 a v = 1 r l = 1k 0v 5v large-signal response 1v/div v s = 5v, 0v 100ns/div 18012 g33 a v = 1 r l = 1k 0v 5v small-signal response 50mv/div v s = 5v, 0v 50ns/div 18012 g34 a v = 1 r l = 1k 0v typical performance characteristics
lt1801/lt1802 14 18012fc applications information circuit description the lt1801/lt1802 have an input and output signal range that covers from the negative power supply to the positive power supply. figure 1 depicts a simpli? ed schematic of the ampli? er. the input stage is comprised of two differential ampli? ers, a pnp stage q1/q2 and an npn stage q3/q4 that are active over the different ranges of common mode input voltage. the pnp differential pair is active between the negative supply to approximately 1.2v below the posi- tive supply. as the input voltage moves closer toward the positive supply, the transistor q5 will steer the tail current i 1 to the current mirror q6/q7, activating the npn differential pair and the pnp pair becomes inactive for the rest of the input common mode range up to the positive supply. also at the input stage, devices q17 to q19 act to cancel the bias current of the pnp input pair. when q1-q2 are active, the current in q16 is controlled to be the same as the current in q1-q2, thus the base current of q16 is nominally equal to the base current of the input devices. the base current of q16 is then mirrored by devices q17-q19 to cancel the base current of the input devices q1-q2. a pair of complementary common emitter stages q14/q15 that enable the output to swing from rail to rail constructs the output stage. the capacitors c2 and c3 form the local feedback loops that lower the output impedance at high frequency. these devices are fabricated on linear technologys proprietary high speed complementary bipolar process. power dissipation the lt1801 ampli? er is offered in a small package, so-8, which has a thermal resistance of 190c/w, ja . so there is a need to ensure that the dies junction temperature should not exceed 150c. junction temperature t j is calculated from the ambient temperature t a , power dissipation p d and thermal resistance ja : t j = t a + (p d ? ja ) the power dissipation in the ic is the function of the sup- ply voltage, output voltage and the load resistance. for a given supply voltage, the worst-case power dissipation p dmax occurs at the maximum supply current and the q4 q18 q17 q16 q6 q3 q7 q10 q1 q13 q15 out q2 q11 q12 q9 q5 v bias i 1 d2 d1 d5 d4 d3 d6 d7 d8 esdd2 esdd1 +in Cin v C esdd3 esdd4 v + v + v C q8 r2 r1 r3 r4 r5 q14 18012 f01 + i 2 + i 3 c2 c c v C + c1 buffer and output bias v + v C q19 figure 1. lt1801/lt1802 simpli? ed schematic diagram
lt1801/lt1802 15 18012fc applications information output voltage is at half of either supply voltage (or the maximum swing is less than 1/2 supply voltage). p dmax is given by: p dmax = (v s ? i smax ) + (v s /2) 2 /r l example: an lt1801 in an so-8 package operating on 5v supplies and driving a 50 load, the worst-case power dissipation is given by: p dmax = (10 ? 4.5ma) + (2.5) 2 /50 = 0.045 + 0.125 = 0.17w if both ampli? ers are loaded simultaneously, then the total power dissipation is 0.34w. the maximum ambient temperature that the part is allowed to operate is: t a = t j C (p dmax ? 190c/w) = 150c C (0.34w ? 190c/w) = 85c input offset voltage the offset voltage will change depending upon which input stage is active. the pnp input stage is active from the negative supply rail to 1.2v from the positive supply rail, then the npn input stage is activated for the remain- ing input range up to the positive supply rail during which the pnp stage remains inactive. the offset voltage is typically less than 75v in the range that the pnp input stage is active. input bias current the lt1801/lt1802 employ a patent-pending technique to trim the input bias current to less than 250na for the input common mode voltage of 0.2v above negative sup- ply rail to 1.2v of the positive rail. the low input offset voltage and low input bias current of the lt1801/lt1802 provide precision performance especially for high source impedance applications. output the lt1801/lt1802 can deliver a large output current, so the short-circuit current limit is set around 50ma to prevent damage to the device. attention must be paid to keep the junction temperature of the ic below the absolute maximum rating of 150c (refer to the power dissipation section) when the output is continuously short circuited. the output of the ampli? er has reverse-biased diodes connected to each supply. if the output is forced beyond either supply, unlimited current will ? ow through these diodes. if the current is transient and limited to several hundred ma and the total supply voltage is less than 12.6v, the absolute maximum rating, no damage will occur to the device. overdrive protection when the input voltage exceeds the power supplies, two pairs of crossing diodes d1 to d4 will prevent the output from reversing polarity. if the input voltage exceeds either power supply by 700mv, diode d1/d2 or d3/d4 will turn on to keep the output at the proper polarity. for the phase reversal protection to perform properly, the input current must be limited to less than 10ma. if the ampli? er is severely overdriven, an external resistor should be used to limit the overdrive current. the lt1801/lt1802s input stages are also protected against a large differential input voltage of 1.4v or higher by a pair of back-back diodes d5/d8 to prevent the emit- ter-base breakdown of the input transistors. the current in these diodes should be limited to less than 10ma when they are active. the worst-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity gain con? guration. in ad- dition, the ampli? er is protected against esd strikes up to 3kv on all pins by a pair of protection diodes on each pin that are connected to the power supplies as shown in figure 1.
lt1801/lt1802 16 18012fc applications information typical applications single 3v supply, 1mhz, 4th order butterworth filter the circuit shown on the ? rst page of this data sheet makes use of the low voltage operation and the wide bandwidth of the lt1801 to create a dc accurate 1mhz 4th order lowpass ? lter powered from a 3v supply. the ampli? ers are con? gured in the inverting mode for the lowest distortion and the output can swing rail-to-rail for maximum dynamic range. also on the ? rst page of this data sheet, the graph displays the frequency response of the ? lter. stopband attenuation is greater than 100db at 50mhz. with a 2.25v p-p , 250khz input signal, the ? lter has harmonic distortion products of less than C 85dbc. worst case output offset voltage is less than 6mv. + C 1/2 lt1801 0.1 i l 0a to 1a v out 0v to 2v v out = 2 ? i l f C3db = 4mhz uncertainty due to v os, i b < 4ma 3v 1k 18012 f02 52.3 52.3 figure 2. fast 1a current sense 500mv/div 0v v s = 3v 50ns/div 18012 f03 figure 3. current sense ampli? er large-signal response fast 1a current sense ampli? er a simple, fast current sense ampli? er in figure 2 is suitable for quickly responding to out-of-range currents. the circuit ampli? es the voltage across the 0.1 sense resistor by a gain of 20, resulting in a conversion gain of 2v/a. the C3db bandwidth of the circuit is 4mhz, and the uncertainty due to v os and i b is less than 4ma. the minimum output voltage is 60mv, corresponding to 30ma. the large-signal response of the circuit is shown in figure 3. capacitive load the lt1801/lt1802 are optimized for high bandwidth, low power and precision applications. they can drive a c a p a c i t i v e l o a d o f a b o u t 7 5 p f i n a u n i t y - g a i n c o n ? g u r a t i o n , and more for higher gain. when driving a larger capaci- tive load, a resistor of 10 to 50 should be connected between the output and the capacitive load to avoid ringing or oscillation. the feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. graphs on capacitive loads indicate the transient response of the ampli? er when driving capacitive load with a speci? ed series resistor. feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. fo r instance, the lt1801/lt1802 in a noninverting gain of 2, setup with two 5k resistors and a capacitance of 5pf (part plus pc board) will prob- ably oscillate. the pole is formed at 12.7mhz that will reduce phase margin by 57 degrees when the crossover frequency of the ampli? er is around 20mhz. a capacitor of 5pf or higher connected across the feedback resistor will eliminate any ringing or oscillation.
lt1801/lt1802 17 18012fc typical applications single supply 1a laser driver ampli? er figure 4 shows the lt1801 used in a 1a laser driver ap- plication. one of the reasons the lt1801 is well suited to this control task is that its 2.3v operation ensures that it will be awaked during power-up and operated before the circuit can otherwise cause signi? cant current to ? ow in the 2.1v threshold laser diode. driving the noninverting input of the lt1801 to a voltage v in will control the turning on of the high current npn transistor, fmmt619 and the laser diode. a current equal to v in /r1 ? ows through the laser diode. the lt1801 low offset voltage and low input + C 1/2 lt1801 v in do not float ir laser infineon sfh495 q1 zetex fmmt619 5v r2 330 r1 1 18012 f04 c1 39pf r3 10 figure 4. single supply 1a laser driver ampli? er 100ma/div 50ns/div 18012 f05 figure 5. 500ma pulse response bias current allows it to control the current that ? ows through the laser diode precisely. the overall circuit is a 1a per volt v-to-i converter. frequency compensation components r2 and c1 are selected for fast but zero- overshoot time domain response to avoid overcurrent conditions in the laser. the time domain response of this circuit, measured at r1 and given a 500mv 230ns input pulse, is shown in figure 5. while the circuit is capable of 1a operation, the laser diode and the transistor are thermally limited due to power dissipation, so they must be operated at low duty cycles.
lt1801/lt1802 18 18012fc package description msop (ms 8 ) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.1 8 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.3 8 (.009 ? .015) typ 0.1016 0.050 8 (.004 .002) 0. 8 6 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.11 8 .004) (note 3) 3.00 0.102 (.11 8 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0. 88 9 0.127 (.035 .005) recommended solder pad layout 0.42 0.03 8 (.0165 .0015) typ 0.65 (.0256) bsc 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.3 8 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.3 8 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn 1203 0.25 0.05 2.3 8 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
lt1801/lt1802 19 18012fc information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . package description s package 14-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) 1 n 2 3 4 .150 ? .157 (3. 8 10 ? 3.9 88 ) note 3 14 13 .337 ? .344 ( 8 .560 ? 8 .73 8 ) note 3 .22 8 ? .244 (5.791 ? 6.197) 12 11 10 9 5 6 7 n/2 8 .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.50 8 ) 45 0 ? 8 typ .00 8 ? .010 (0.203 ? 0.254) s14 0502 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.4 8 3) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc .245 min n 123 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt1801/lt1802 20 18012fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2002 lt 0309 rev c ? printed in usa related parts typical application part number description comments lt1399 triple 300mhz current feedback ampli? er 0.1db gain flatness to 150mhz, shutdown lt1498/lt1499 dual/quad 10mhz, 6v/s rail-to-rail input and output c-load ? op amps high dc accuracy, 475v v os(max) , 4v/c max drift lt1630/lt1631 dual/quad 30mhz, 10v/s rail-to-rail input and output op amps high dc accuracy, 525v v os(max) , 70ma output current, max supply current 4.4ma per ampli? er lt1800 80mhz, 25v/s low power rail-to-rail input/output precision op amp single version of lt1801/lt1802 lt1806/lt1807 single/dual 325mhz, 140v/s rail-to-rail input and output op amps high dc accuracy, 550v v os(max) , low noise 3.5nv/ hz , low distortion C80db at 5mhz, power-down (lt1806) lt1809/lt1810 single/dual 180mhz rail-to-rail input/output op amps 350v/s slew rate, low distortion C90dbc at 5mhz, power-down (lt1809) c-load is a trademark of linear technology corporation low power high voltage ampli? er certain materials used in optical applications have charac- teristics that change due to the presence and strength of a dc electric ? eld. the voltage applied across these materials should be precisely controlled to maintain desired proper- ties, sometimes as high as 100s of volts. the materials are not conductive and represent a capacitive load. the circuit of figure 6 shows the lt1801 used in an ampli- ? er capable of a 250v output swing and providing precise dc output voltage. when no signal is present, the op + C 1/2 lt1801 5v 10k 10k q3 q1 4.99k 1k 1k C130v 18012 f06 4.99k q5 q7 q2 q4 q6 q8 r1 2k r2 2k r5 2k r4 2k r7 2k r6 2k r3 200k 0.1f c1 39pf c2 8pf 150v v out v in material under electric field 100pf 130v 5v 5v a v = v out /v in = C100 130v supply i q = 130a output swing = 128.8v output offset ? 20mv output short-circuit current ? 3ma 10% to 90% rise time ? 8 s, 200v output step small-signal bandwidth ? 150khz q1, q2, q7, q8: on semi mpsa42 q3, q4, q5, q6: on semi mpsa92 figure 6. low power, high voltage ampli? er figure 7. large-signal time domain response of the ampli? er v in 2v/div v out 50v/div 10s/div 18012 f07 amp output sits at about mid-supply. transistors q1 and q3 create bias voltages for q2 and q4, which are forced into a low quiescent current by degeneration resistors r4 and r5. when a transient signal arrives at v in , the op amp output moves and causes the current in q2 or q4 to change depending on the signal polarity. the current, limited by the clipping of the lt1801 output and the 3k of total emitter degeneration, is mirrored to the output devices to drive the capacitive load. the lt1801 output then returns to near mid-supply, providing the precise dc output voltage to the load. the attention to limit the current of the output devices minimizes power dissipation thus allowing for dense layout, and inherits better reliability. figure 7 shows the time domain response of the ampli? er providing a 200v output swing into a 100pf load.

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